Semiconductor integrated circuit device

ABSTRACT

Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuitdevice, and particularly to a technology effective for application to adevice wherein protruded electrodes such as solder bumps or the like forboard packaging are formed on a semiconductor substrate.

BACKGROUND ART

As semiconductor integrated circuit devices (hereinafter called simply“flip-chip semiconductor integrated circuit devices”) wherein protrudedelectrodes such as solder bumps or the like are formed, there are knownUnexamined Patent Publication No. Hei 5(1993)-218042, Unexamined PatentPublication No. Hei 8(1996)-250498, and U.S. Pat. No. 5,547,740. Each ofthese Publications shows one basic form of the flip-chip semiconductorintegrated circuit device.

In the flip-chip semiconductor integrated circuit device described ineach of the above Publications, rewirings are routed from bonding padsof a chip thereof, for example, and bump electrodes connected to therewirings are placed on the surface of the chip in an array (area array)form. The bump electrodes disposed in such an area array form areexposed from a surface protective film. It is thus possible to enlargethe interval between the adjacent bump electrodes and facilitate theboard packaging that bump electrodes are connected to wirings on aprinted circuit board. Further, a low-cost printed circuit board wide inwiring interval can be utilized. In such a flip-chip semiconductorintegrated circuit device, the bump electrodes are terminals directlyconnected to the printed circuit board. Only the bump electrodes areexposed and the bonding pads of the semiconductor chip are covered withan insulating film or a protective film. Therefore, the bump electrodescorrespond to external connecting terminals such as lead pins of apackage such as a QFP or the like.

In the above-described flip-chip semiconductor integrated circuitdevice, there is a tendency to more and more increase the scale of eachinternal circuit for the purpose of improvements in function. Whilst thesize of one semiconductor chip is made large with the increase incircuit scale, a circuit's wiring width becomes small. Therefore, forexample, in a clock-operated semiconductor integrated circuit device, asignal delay is developed while a clock supplied from an externalterminal is being transmitted through an internal wiring. A skew occursbetween clocks supplied to individual internal circuits and a timingmargin for accommodating it is required, thus interfering with thetransition of the clock to a high frequency. A problem arises in thatwhen a source voltage is stepped down in association with low powerconsumption, device micro-fabrication, etc. and set as an operatingvoltage for each internal circuit, it is necessary to provide aplurality of step down voltage generators for the purpose of preventinga voltage loss in the internal wiring, and hence current consumption atsuch step down circuit units will increase and a circuit scale willincrease.

An object of the present invention is to provide a semiconductorintegrated circuit device capable of speeding up its operation andenabling circuit's rational arrangements. Another object of the presentinvention is to provide a semiconductor integrated circuit devicecapable of enhancing the degree of freedom of the layout of circuitslying within a chip in a simple configuration. The above, other objects,and novel features of the present invention will become apparent fromthe description of the present specification and the accompanyingdrawings.

DISCLOSURE OF THE INVENTION

A summary of a typical one of the inventions disclosed in the presentapplication will be described in brief as follows: Circuit elements andwirings constituting a circuit, and first electrodes electricallyconnected to such a circuit are provided on one main surface of asemiconductor substrate. An organic insulating film is formed on thecircuit except for openings on the surfaces of the first electrodes.First and second external connecting electrodes are provided on theorganic insulating film, and a conductive layer for electricallyconnecting the first and second external connecting electrodes and thefirst electrode is mounted onto the organic insulating film.

A summary of another typical one of the inventions disclosed in thepresent application will be described in brief as follows: Circuitelements and wirings constituting a circuit, and first and secondelectrodes electrically connected to such a circuit are provided on onemain surface of a semiconductor substrate. An organic insulating film isformed on the circuit except for openings on the surfaces of the firstand second electrodes, and a conductive layer for electricallyconnecting the first and second electrodes is placed on the organicinsulating film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1(A) and 1(B) are schematic configurational views showing oneembodiment of a semiconductor integrated circuit device according to thepresent invention;

FIG. 2 is a plan view showing one embodiment of the semiconductorintegrated circuit device according to the present invention;

FIG. 3 is a schematic layout diagram illustrating one embodiment of aDRAM to which the present invention is applied;

FIG. 4 is a block diagram showing one embodiment of a clock input unitof the semiconductor integrated circuit device according to the presentinvention;

FIG. 5 is a schematic cross-sectional view illustrating one embodimentof the semiconductor integrated circuit device according to the presentinvention;

FIG. 6 is a schematic plan view depicting one embodiment of thesemiconductor integrated circuit device according to the presentinvention;

FIG. 7 is a block diagram showing one embodiment of the semiconductorintegrated circuit device according to the present invention;

FIG. 8 is a schematic plan view illustrating one embodiment of thesemiconductor integrated circuit device according to the presentinvention;

FIG. 9 is a schematic cross-sectional view showing one embodiment of thesemiconductor integrated circuit device according to the presentinvention;

FIG. 10 is a schematic plan view illustrating another embodiment of asemiconductor integrated circuit device according to the presentinvention;

FIGS. 11(A) and 11(B) are schematic configurational views showing afurther embodiment of a semiconductor integrated circuit deviceaccording to the present invention;

FIG. 12 is a schematic layout diagram illustrating another embodiment ofa DRAM to which the present invention is applied;

FIG. 13 is a block diagram showing one embodiment of a clock input unitof the DRAM shown in FIG. 12;

FIG. 14 is a plan view illustrating a still further embodiment of asemiconductor integrated circuit device according to the presentinvention;

FIG. 15 is a schematic cross-sectional view for describing oneembodiment of a method for manufacturing rewiring, according to thepresent invention;

FIG. 16 is a cross-sectional view of another embodiment illustrative ofrewirings provided in a semiconductor integrated circuit deviceaccording to the present invention;

FIG. 17 is a vertical cross-sectional view of a device structure, whichshows one embodiment illustrative of a logic circuit and an externalinput/output circuit formed on a semiconductor chip that constitutes asemiconductor integrated circuit device according to the presentinvention;

FIGS. 18(A) to 18(D) are cross-sectional views of the device structure,for describing some of one embodiment of a method of manufacturingrewirings for a semiconductor integrated circuit device according to thepresent invention;

FIGS. 19(E) to 19(G) are cross-sectional views of the device structure,for describing the remaining part of one embodiment of the method ofmanufacturing the rewirings for the semiconductor integrated circuitdevice according to the present invention;

FIG. 20 is a perspective view at one step, for describing amanufacturing process of a flip-chip semiconductor integrated circuitdevice according to the present invention;

FIG. 21 is a perspective view at another step, for describing themanufacturing process of the flip-chip semiconductor integrated circuitdevice according to the present invention;

FIG. 22 is a perspective view at a further step, for describing themanufacturing process of the flip-chip semiconductor integrated circuitdevice according to the present invention;

FIG. 23 is a perspective view at a still further step, for describingthe manufacturing process of the flip-chip semiconductor integratedcircuit device according to the present invention;

FIG. 24 is a perspective view at a still further step, for describingthe manufacturing process of the flip-chip semiconductor integratedcircuit device according to the present invention;

FIG. 25 is a flowchart for describing manufacturing process flowssubsequent to a rewiring forming process step employed in the flip-chipsemiconductor integrated circuit device according to the presentinvention;

FIGS. 26(A) and 26(B) are schematic cross-sectional views showing astill further embodiment of a semiconductor integrated circuit deviceaccording to the present invention;

FIGS. 27(A) and 27(B) are schematic configurational views illustrating astill further embodiment of a semiconductor integrated circuit deviceaccording to the present invention;

FIG. 28 is a plan view showing a still further embodiment of asemiconductor integrated circuit device according to the presentinvention; and

FIG. 29 is a plan view showing a still further embodiment of asemiconductor integrated circuit device according to the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

Preferred embodiments of the present invention will hereinafter bedescribed in detail with reference to the accompanying drawings.

FIGS. 1(A) and 1(B) are schematic configurational views showing oneembodiment of a semiconductor integrated circuit device according to thepresent invention. A sectional portion is shown in FIG. 1(A), and a planportion is shown in FIG. 1(B), respectively. In the semiconductorintegrated circuit device showing the present embodiment, unillustratedcircuit elements and wirings are formed on one main surface side of asemiconductor chip 06. Pads 04 are formed of the top-layer wiring ofthese wirings. An organic insulating film 02 corresponding to a firstlayer is formed except for openings for the pads 04. Although notrestricted in particular, the organic insulating film 02 is formed ofpolyimide.

A rewiring layer 05 used as a conductive layer, which electricallyconnects between at least two pads 04 formed on the main surface side ofthe semiconductor chip 06, is formed on the organic insulating filmcorresponding to the first layer formed of the polyimide. An organicinsulating film 01 corresponding to a second layer is formed except foropenings in which bump electrodes 03 are formed within the surface ofthe rewiring layer 05. The bump electrodes are provided at least twowith respect to one rewiring layer 05.

The rewiring layer 05 employed in the present embodiment is not intendedfor substitution for lead pins of a general IC package by simply routingrewirings from bonding pads of a semiconductor chip to increaseintervals between adjacent bump electrodes and connecting the bumpelectrodes to wirings on a printed circuit board. The rewiring layer 05is intended to act as a wiring that interconnects between the two bumpelectrodes 03 and is connected to two pads (bonding pads) provided on asemiconductor chip. The configuration of such a rewiring layer 05becomes beneficial as power supply means to be next described.

Although not restricted in particular, a top wiring layer 07 forconnecting the two pads 04 is formed on the main surface of thesemiconductor chip 06. The circuit elements formed on the main surfaceside of the semiconductor chip 06, for example, are supplied withoperating voltages such as a source voltage, etc. through the use of thetop wiring layer 07.

A plan view of one embodiment of a semiconductor integrated circuitdevice according to the present invention is shown in FIG. 2. Althoughnot restricted in particular, the semiconductor integrated circuitdevice showing the present embodiment is intended for a dynamic RAM(Random Access Memory). A layout of rewirings, and bump electrodes andpads connected thereto is shown therein.

In the same drawing, the bump electrodes are respectively indicated by ◯and the pads are respectively indicated by small □. These bumpelectrodes and pads are interconnected with each other by theircorresponding rewirings. The rewirings 05 are divided into two types fora DC voltage and an AC signal according to the functions thereof. Onewiring layer 605 illustratively shown is identical to the rewiringemployed in the conventional wafer/level CSP (chip size package) andconnects one bump electrode and one pad to each other in a one-to-onecorrespondence. Each wiring layer 605 is used for the input of anaddress and a control signal and the input/output of data. Theseindividual signal lines 605 are reduced in parasitic capacity and makeuse of rewiring layers each having a wiring width formed thin relativelyin association with a plurality of pads provided in high density inorder to transfer digital signals transmitted through the signal linesat high speed.

In the present embodiment, the rewiring layer 05 is used to allow thesupply of power at low impedance. In the same drawing, a rewiring layer105 having a thick wiring width, which is obtained by extending the leftend of the semiconductor chip upwards and downwards and bending the sametoward the center at upper and lower portions thereof, is provided tosupply a source voltage VDD. The rewiring 105 is provided with threebump electrodes at its upper portion, one bump electrode in the centerthereof, and three bump electrodes at its lower portion. The supply ofthe source voltage VDD is performed from seven places or points in totalas viewed from the outside. The rewiring 105 comprises portions eachhaving a thick wiring width, which is to serve as a main line, andportions which branch therefrom and are connected to a plurality of padsof the semiconductor chip at plurality of places or points throughrelatively thinner wirings. The supply of the source voltage VDD fromthese plural pads to circuit elements is carried out through such atop-layer wiring as described above.

A rewiring layer 205 having a thick wiring width, which is obtained byextending the right end of the semiconductor chip upwards and downwardsand folding the same toward the center at upper and lower portionsthereof, is provided to supply a ground potential VSS in a circuit. Therewiring layer 205 is provided with two bump electrodes at its upperportion, one bump electrode in the center thereof, and three bumpelectrodes at its lower portion. The supply of the ground potential VSSin the circuit is performed from six places or points in total as viewedfrom the outside. The rewiring 205 comprises portions each having athick wiring width, which is to serve as a main line, and portions whichbranch therefrom and are connected to a plurality of pads of thesemiconductor chip at plurality of places or points through relativelythinner wirings. The supply of the circuit ground potential VSS fromthese plural pads to circuit elements is carried out through such atop-layer wiring as described above. Using the rewiring layers eachhaving the thick wiring width for the supply of the source voltages VDD,VSS, etc. yields the formation of a relatively large parasiticcapacitance contrary to each signal line 605 referred to above. In thecase of the source or power supply lines VDD and VSS, parasiticcapacitances provided therefor will contribute to voltage stabilization.

In the present embodiment, power supply paths are provided independentlyfor an output circuit to lessen the transfer of relatively large sourcenoise produced in the output circuit to an input circuit and an internalcircuit. Namely, each of rewiring layers 305 is used to supply a circuitground potential VSSQ to the output circuit. The rewiring layers 305 areprovided on the semiconductor chip with being divided into four and areprovided with their corresponding bump electrodes for supplying theground potential VSSQ thereto. These rewiring layers 305 areinterconnected with one another by wirings placed on a printed circuitboard or mounting board through the bump electrodes and supplied withthe same ground potential VSSQ.

A rewiring layer 405 for supplying a source voltage VDDQ for the outputcircuit is disposed so that the central portion of the semiconductorchip is extended upwards and downwards. The rewiring layer 405 isprovided with bump electrodes provided two by two at upper and lowerends and one bump electrode provided in its central portion and issupplied with the source voltage VDDQ from five points in total.

In the present embodiment, rewiring layers are used even for signallines for transferring an AC signal in addition to the utilization ofthe rewiring layers for the purpose of the supply of the above-describedDC voltage. A rewiring layer 505 is one for transmitting a clock CLK andis provided with the clock CLK from a bump electrode provided in thecentral portion of the semiconductor chip. The rewiring layer 505 servesso as to transfer the clock CLK to a pad provided in the central portionof the semiconductor chip and pads provided at upper and lower endsthereof. Thus, the clock CLK is distributed to the semiconductor chipformed in a relatively large size for the purpose of large storagecapacity through the use of the rewiring layer 505 low in resistancevalue. Further, the skew of the clock CLK in the internal circuit isreduced and the speeding up of operation is enabled.

Although not restricted in particular, the DRAM chip according to thepresent embodiment has four memory banks and is a synchronous DRAM or asynchronous DRAM having a DDR configuration. Memory accesses are madefrom the four memory banks in 64-bit units. The input/output circuitsare configured as sixty-four in number and placed side by side in upperand lower directions at the central portion of the semiconductor chip.Thus, the rewiring layers 305 and 405 used as the power lines forsupplying the operating voltages VDDQ and VSSQ are provided as describedabove in association with the input/output circuits.

As described above, the sixty-four input/output circuits aredispersively disposed in the center of the semiconductor chip with arelatively long distance. Therefore, the distance between the adjacentinput/output circuits placed at the upper and lower ends becomes longand hence the delay of propagation of the clock CLK appears as skew asit is, thereby interfering with the speeding up of the operation. Sincethe present embodiment is intended to provide the bump electrodes forsupplying the clock CLK in the center and make branches upward anddownward therefrom so as to distribute the clock CLK through therewiring 505, a propagation delay in the supply path of the clock can belessened by distributing the clock at a distance corresponding to onehalf the distance between the input/output circuits disposed at theupper and lower ends and making use of the rewiring 505 low inresistance. Namely, the clock skew takes the maximum between the circuitsupplied with the clock from each of the pads provided adjacent to thebump electrodes and the circuit supplied with the clock from each of thepads provided at both ends. Thus, such a clock skew can greatly bereduced owing to the utilization of the rewiring 505 referred to above.

A schematic layout diagram of one embodiment of a DRAM to which thepresent invention is applied, is shown in FIG. 3. The layout of the DRAMaccording to the present embodiment corresponds to the rewirings andpads of the DRAM shown in FIG. 2. In the same drawing, memory arrays ormemory mats 14 are provided with being divided into plural parts.Input/output circuits are dispersively disposed in a vertical centralportion of a semiconductor chip as described above, and input/outputcontrol circuits 13 are provided in association therewith. Theinput/output control circuits 13 are provided four by four with respectto the respective two separated memory arrays 14 so as to interpose thevertical central portion of the chip therebetween. Thus, oneinput/output control circuit 13 takes charge of the eight input/outputcircuits.

Of the input/output control circuits 13 provided four by four inassociation with the left and right memory arrays, ones divided two bytwo in the upper and lower directions are respectively set as pairs, andone clock input buffer 11 is assigned to each pair. Further, one clockinput pads CLKU and CLKD are provided with respect to the two clockbuffers 11 provided adjacent to each other from sided to side. A clockinput pad CLKC is provided even in the center of the chip.

Theses clock input pads CLKU, CLKC and CLKD are interconnected with oneanother by means of a rewiring 12 for clock input. The rewiring 12 isconnected even to a solder bump electrode 10 for clock input. Owing tosuch a configuration, a clock CLK inputted from the solder bumpelectrode 10 for clock input is transmitted to the clock input padsCLKC, CLKU and CLKD through the rewiring 12.

The clock CLK is transferred from the clock input pads CLKU, CLKC andCLKD to the corresponding clock input buffer 11 through top metal wiringlayers 15 of the DRAM chip, which comprise aluminum or the like.Although not restricted in particular, internal clock signals formed orproduced from the respective clock input buffers 11 are similarlytransmitted to their corresponding input/output control circuits 13through the top metal wiring layers 15 of the DRAM chip, which comprisealuminum or the like. Although not restricted in particular, the clockinput buffer 11 provided in association with the clock input pad CLKCforms internal clock signals supplied to an unillustrated address inputcircuit, a data input circuit or input circuits or the like such ascontrol signal input circuits or the like for RAS, CAS, WE, etc.

A block diagram of one embodiment of a clock input unit of asemiconductor integrated circuit device according to the presentinvention is shown in FIG. 4. The present embodiment corresponds to theclock input circuit of the DRAM shown in FIG. 3.

A clock input bump electrode 10 is connected to clock input pads CLKU,CLKC and CLKD by means of a rewiring 12. A clock supplied from the clockinput pad CLKC is transmitted to the input of a clock input buffer 11.An internal clock outputted from the clock input buffer 11 istransferred to a read/write control circuit 16. If the read/writecontrol circuit 16 receives instructions for a read operation accordingto an unillustrated command, it forms a read control signal READ.

The read control signal READ is set as a control signal used for each ofthe clock input buffers 11 provided in association with the clock inputpads CLKU and CLKD. If the read control signal READ is regarded as aneffective level, then the clock input buffers 11 form or produce outputregister clocks QCLK0 through QCLK3 from the clock signals inputted viathe clock input pads CLKU and CLKD and transfer them to output registercircuits 17 included in input/output control circuits 13, respectively.The output register circuits 17 take in or capture read data dataaccording to the output register clocks QCLK0 through QCLK3 and transferoutput signals to input/output pads 19 through output buffer circuits18, respectively. These input/output pads 19 are connected toinput/output bump electrodes through unillustrated rewiringsrespectively.

A schematic cross-sectional view of one embodiment of the semiconductorintegrated circuit device according to the present invention is shown inFIG. 5. Although not restricted in particular, the present embodimentcorresponds to the clock input unit shown in FIG. 3 or FIG. 4.

Since the semiconductor integrated circuit device showing the presentembodiment is formed up to a package according to a wafer process asshown in FIGS. 20 through 24 to be described later, the rewirings andbump electrodes might be called “WPP (an abbreviation of Wafer ProcessPackage) wirings (layer) or WPP bumps”. The following description willbe made using the WPP wiring layers or WPP bumps. The WPP bumps areformed on the WPP wiring layer and electrically connected to oneanother. The WPP wiring layer adheres onto the organic insulating filmnot shown and is connected to a metal pad PAD on a chip at its opening.The metal PAD is electrically connected to a circuit 1 through a metalwiring corresponding to a top layer on the chip. Although not restrictedin particular, the metal PAD corresponds to the clock input pad CLKC,and the circuit 1 corresponds to each of the clock input buffers 11.

The WPP wiring layer further extends from a metal PAD portioncorresponding to the circuit 1 so as to connect to a metal PADcorresponding to a circuit 2 at its opening. The metal PAD and thecircuit 2 are connected to each other by means of a metal wiring on thechip in the same manner as described above. The circuit 2 is controlledin operation according to the read control signal READ and constitutesone input buffer 11 which receives therein a clock signal inputted viaan unillustrated clock input pad CLKU or CLKD.

A schematic plan view of one embodiment of the semiconductor integratedcircuit device according to the present invention is shown in FIG. 6.Although not restricted in particular, the present embodimentcorresponds to the clock input unit shown in FIG. 3 or FIG. 4.

A clock signal WPP bump similar to the above is formed on a WPP wiringlayer to provide electrical connections. The WPP wiring layer is mountedonto the organic insulating film not shown and is connected to a CLK PAD(clock pad) on a chip at its opening. The CLK PAD is connected to aclock buffer circuit by a CLK wiring that comprises a metal wiring of atop layer on the chip, and is connected to a peripheral circuit by asimilar wiring. The peripheral circuit constitutes the read/writecontrol circuit 16, for example.

The WPP wiring layer is extended so as to further branch up and downfrom the CLK PAD unit corresponding to the clock buffer circuit and isconnected to two CLK PADs corresponding to the CLKU and CLKD at theiropenings. These CLK PADs are connected to their corresponding peripheralcircuits by metal wirings on the chip in a manner similar to the above.The peripheral circuits are controlled in operation according to theread control signal READ and respectively constitute output controlcircuits 13 each including an input buffer 11 receiving a clock signalinputted via an unillustrated clock input pad CLKU or CLKD.

A block diagram of one embodiment of the semiconductor integratedcircuit device according to the present invention is shown in FIG. 7.Although not restricted in particular, the present embodimentcorresponds to the clock input unit shown in FIG. 3 or FIG. 4.

A clock signal WPP bump similar to the above is formed on a WPP wiringlayer to provide electrical connections. The WPP wiring layer is mountedonto the organic insulating film not shown and is connected to clocksignal WPP bumps at their openings. The WPP wiring layer (CLK wiring) isconnected to pads PADs associated with clock buffer circuits forperipheral circuits to which the WPP wiring layer is distributed.

In present embodiment, even up to pads PADs corresponding to inputportions of clock buffers in the peripheral circuits to which the WPPwiring layer is distributed, are introduced from the clock signal WPPbump by means of clock wirings low in resistance, which comprise theabove-described WPP wirings (rewirings). Therefore, signal delaysthereat become small and mutual clock skews are also reduced. Therespective pads PADs correspond to the respective pads illustrated inthe embodiments shown in FIGS. 3 through 6. Thus, the respectiveperipheral circuits are associated with the read/write control circuit16 and each of the output circuits 13.

A schematic plan view of one embodiment of the semiconductor integratedcircuit device according to the present invention is shown in FIG. 8.The present invention is intended for a distributed example of externalsources or power supplies. Power supply paths for a source voltage VDDand a circuit ground potential VSS are shown for respective circuitsformed on a semiconductor chip.

A pair of WPP wirings is provided so that the left and right ends of thesemiconductor chip extend upward and downward. Of the pair of WPPwirings, the WP wiring placed on the left side serves so as to supplythe source voltage VDD although not restricted in particular. At theupper and lower ends and the central portion of the WPP wiring, WPPbumps are respectively provided at protrusions respectively provided soas to branch to the middle side of the chip. The source voltage VDD issupplied from the three points of the upper and lower ends and thecentral portion referred to above. Further, the WPP wiring placed on theright side serves so as to supply the circuit ground potential VSS. Atthe upper and lower ends and the central portion of the WPP wiring, WPPbumps are respectively provided at protrusions respectively provided soas to branch to the middle side of the chip. The circuit groundpotential VSS is supplied from three points of the upper and lower endsand the central portion thereof.

Of the WPP wiring layer for the source voltage VDD, although notrestricted in particular, a WPP wiring, which has further extended fromthe WPP bump to the central portion of the chip on the lower end side,is formed and connected to its corresponding pad VDD PAD. The pad VDDPAD is connected to a wiring on the chip and serves so as to supply thesource voltage VDD to each circuit element formed on the semiconductorchip through such an on chip wiring. Incidentally, in order to reducesource impedance, thin WPP wirings are caused to suitably branch offfrom the thick WPP wiring constituting the main line and are connectedto their corresponding pads VDD PADs similar to the above. Such VDD PADsmay be interconnected with one another by means of the on chip wiring.

Of the WPP wiring layer for the circuit ground potential VSS, a WPPwiring, which has further extended from the WPP bump to the centralportion of the chip on the upper end side, is formed and connected toits corresponding pad VSS PAD. The pad VSS PAD is connected to a wiringon the chip and serves so as to supply the circuit ground potential VSSto each circuit element formed on the semiconductor chip through such anon chip wiring. Incidentally, in order to reduce source impedance, thinWPP wirings are caused to suitably branch off from the thick WPP wiringconstituting the main line and are connected to their corresponding padsVSS PADs similar to the above. Such VSS PADs may be interconnected withone another by means of the on chip wiring.

A schematic cross-sectional view of one embodiment of the semiconductorintegrated circuit device according to the present invention is shown inFIG. 9. Although not restricted in particular, the present embodiment isintended for the power supply path used for the source voltage VDD (orcircuit ground potential VSS) employed in the embodiment of FIG. 7.

WPP bumps are formed on a WPP wiring layer (VDD) to provide electricalconnections. The WPP wiring layer is mounted onto the organic insulatingfilm not shown, and the WPP bumps equal to the three in total areprovided thereover. The WPP wiring layer is connected to itscorresponding pad VDD PAD at an opening defined in the organicinsulating film. The pad VDD PAD is connected to an on chip wiring,i.e., a metal wiring corresponding to a top layer and serves so as tosupply the source voltage VDD to each of unillustrated circuit elementsthrough such an on chip wiring.

A schematic plan view of another embodiment of a semiconductorintegrated circuit device according to the present invention is shown inFIG. 10. The present invention is intended for a distributed example ofinternal sources. A power supply path for an internal voltage VDDIobtained by deboosting or decreasing a source voltage VDD supplied fromoutside is shown for respective circuits formed on a semiconductor chip.

A WPP wiring is provided so that the right and left ends and the lowerend of the semiconductor chip are extended. The WPP wiring serves as asource or power wiring used for supplying the internal voltage VDDI. Ofthe WPP wiring, the WPP wiring extended in the horizontal direction atthe lower end is provided with a branch and connected to a pad VDDI PADtherethrough. The pad VDDI PAD serves so as to transfer a stepped-downvoltage VDDI formed by a step down circuit through an on chip wiring.Thus, such a WPP wiring layer that the right and left ends and the lowerend are extended, surrounds the semiconductor chip to transfer thestepped-down voltage VDDI. Further, the stepped-down voltage VDDI issupplied to peripheral circuits with such a voltage VDDI as an operatingvoltage, through pads VDDI PADs provided in plural places.

A WPP bump for VDD is provided for the supply of the source voltage VDDto the step-down circuit and connected to its corresponding pad VDD PADby the WPP wiring layer. The pad VDD PAD is connected to an on chipwiring, and hence the source voltage VDD is supplied to the step-downcircuit through such an on chip wiring. When a circuit with the sourcevoltage VDD as an operating voltage is placed on the semiconductor chipalthough it is not shown in the drawing, it is connected via the WPPwiring layer connected to the WPP bump for VDD to the pad VDD PADprovided in association with the circuit having need of it. Thus, thesupply of the source voltage VDD is performed in a manner similar to thestep-down circuit.

A schematic configurational view of a further embodiment of asemiconductor integrated circuit device according to the presentinvention is shown in FIGS. 11(A) and 11(B). In addition to theprovision of a WPP wiring layer in a one-to-one correspondence between aWPP bump and a pad PAD, the WPP wiring layer is used as parts of asignal line and a power supply line. In this case, it is necessary toelectrically isolate wirings different from one another and place thewirings in crossed form. Multilayering the WPP wiring makes it easy tocross the wirings while they are being electrically isolated in thisway. However, a process for manufacturing the WPP wiring becomescomplex, thus increasing its manufacturing cost.

The present embodiment is intended to, when a WPP wiring extended in ahorizontal direction as shown in FIG. 11(A) and a wiring extended in avertical direction orthogonally to it are electrically isolated fromeach other and placed so as to intersect each other, place the wiringextended in the vertical direction on an on chip wiring at itsintersection and separate it therefrom as shown in FIG. 11(B). Namely,in FIG. 11(A), a WPP bump used for an external input signal, which isprovided on the upper side of the WPP wiring layer extended in thehorizontal direction, is connected to the on chip wiring formed on thelower side with an organic insulating film of the WPP wiring layerextended in the horizontal direction being interposed therebetween, viathe pad PAD through the use of the WPP wiring. Such an on chip wiring isintroduced into the corresponding pad PAD through the lower side of theWPP wiring layer extended in the horizontal direction. The on chipwiring is connected to its corresponding WPP wiring again therefrom andintersects another on chip wiring, followed by connection to the pad PADfor the external input signal.

Even if the WPP wiring layer extended in the horizontal direction inFIG. 11(A) constitutes a source or power line for transferring theinternal stepped-down voltage and external source voltage, the inputsignal line can be provided so that such a power line intersects it asin the present embodiment. Further, the degree of freedom of the layoutof circuits formed on a semiconductor chip can be increased. Namely,signal lines used for the input of address signals and data and theoutput of data, which are in need of a high-speed operation, are placedwith WPP bumps and pads being respectively provided with relativelyshort distances therebetween. A WPP bump used for signal input, whichcorresponds to a signal line being in no need of high-speed signaltransfer as in the case of a signal line for performing switchingbetween operation modes, is formed in a space area so as to avoid theportions where the WPP bumps corresponding to the input of the addresssignals and data and the output of data are formed. Such WPP bumps maybe formed of the WPP wiring including the on chip wiring at theabove-described intersection.

A schematic layout diagram of another embodiment of a DRAM to which thepresent invention is applied, is shown in FIG. 12. The layout of theDRAM according to the present embodiment corresponds to the rewiringsand pads of the DRAM shown in FIG. 2 except for a clock input system.Namely, memory arrays or memory mats 14 are provided so as to be dividedinto plural form in the same manner as described above. Sixty-fourinput/output circuits are dispersively disposed in a vertical centralportion of a semiconductor chip in a manner similar to the above.Input/output control circuits 114 are provided in association with theinput/output control circuits. The input/output control circuits 114 areprovided four by four with respect to the respective two separatedmemory arrays 14 so as to interpose the vertical central portion of thechip therebetween. Thus, one input/output control circuit 114 takescharge of the eight input/output circuits.

The four-by-four provided output control circuits 114 provided inassociation with the right and left memory arrays are respectivelyprovided with pads CLKU1 through CLKU4 and CLKD1 through CLKD4 for theinput of a clock supplied thereto. An internal clock formed by a clockreproducing circuit 110 is transferred to each of the pads through theuse of a rewiring 12. A clock CLK inputted from a solder bump electrode10 for clock input is sent via the rewiring 12 to a pad CLKC, from whichthe clock is transmitted to the clock reproducing circuit 110 through anon chip wiring 15. The clock reproducing circuit 110 comprises a PLLcircuit or a DLL or SMD circuit and forms or produces an internal clocksignal corresponding to the clock CLK supplied from outside. Thethus-formed internal clock signal is sent via the on chip wiring to apad CLK2 from which the clock is distributed to the respective clockinput pads CLKU1 through CLKU4 and CLKD1 through CLKD4 by means of therewiring 12.

A block diagram of one embodiment of a clock input unit of the DRAMshown in FIG. 12 is shown in FIG. 13. A bump electrode 10 for clockinput is connected to a clock input pad CLKC by means of a rewiring 12.A clock supplied from a clock input pad CLKC is transferred to a clockreproducing circuit 110 by an on chip wiring. The clock reproducingcircuit 110 comprises a clock synchronous circuit like the PLL circuit,DLL circuit or SMD circuit and forms an internal clock signalsynchronized with the clock supplied from the clock input bump electrode10 so as to have a predetermined phase difference.

If, for example, the clock supplied from outside is sent to eachinternal circuit as it is, then an internal clock will lag by a signaldelay developed in an input buffer circuit having received the clocksupplied from outside. The PLL circuit, DLL circuit or SMD circuit isused to compensate for such a phase delay.

The PLL (Phase-Locked Loop) circuit causes a phase comparator to detecta phase difference (frequency difference) between a clock supplied fromoutside and a clock formed or produced by a voltage-controlledoscillator circuit such as a VCO or the like by comparison, and producessuch a control signal as to allow the two to coincide with each other,thereby controlling the VCO. In other words, the PLL circuit is capableof inserting a delay circuit formed of a replica circuit correspondingto the input buffer within the PLL loop for the clocks compared by thephase comparator, thereby canceling the phase difference between theexternal clock and the internal clock or greatly forming the delay timelarger than a delay time in the input buffer to thereby cause the phaseof the internal clock to lead that of the external clock.

When, for example, an internal clock advanced in phase is generated, thePLL circuit can compensate for a signal delay of an output circuit uponthe output of data according to such an internal clock and output datain synchronism with the clock supplied from the outside. If an Ndividing circuit is inserted within the PLL loop, then the PLL circuitcan form or produce an internal clock whose frequency is obtained bymultiplying that of the external clock by N.

The DLL (Delay Locked Loop) circuit compares a clock delayed by avariable delay circuit and a clock inputted with a delay of one periodor cycle through the use of a phase comparator and controls a delay timeof the variable delay time so that the two coincide with each other.Inserting a delay circuit formed of a replica circuit corresponding toeach input buffer for clock input for the clocks compared by the phasecomparator in a manner similar to the PLL circuit makes it possible tocancel or eliminate the phase difference between the external clock andthe internal clock. Alternatively, the delay time is formed larger thana delay time of the input buffer to allow the phase of the internalclock to lead that of the external clock.

The SMD (Synchronous Mirror Delay) circuit is of a clock synchronouscircuit which does not include a feedback loop, like the PLL circuit andthe DLL circuit. The time (lock time) necessary for synchronization isshort like 2 to 3 cycles. The lock time can be shortened by measuringthe cycle of an input clock as the number of stages of delay circuits.This measuring circuit is one for measuring a delay time per stagecorresponding to a constituent element or component of each delaycircuit as time resolution. In general, this time becomes equivalent toabout a delay time corresponding to two stages of CMOS invertercircuits. As an example of the clock synchronous circuit using such anSMD, there is known one disclosed in Unexamined Patent Publication No.Hei 8(1996)-237091.

The internal clock generated by the clock reproducing circuit 110 isintroduced via the on chip wiring into the pad CLK2 from which theinternal clock is distributed to clock input pads CLKU1 through CLKU8 ofinput/output control circuits 114 by rewirings 12. The input/outputcontrol circuit 114 includes, for example, an address input pad 113, anaddress input buffer 112 which receives an address signal inputted fromthe address input pad 113, and an address input register 111 for takingin or capturing the address signal. The internal clock is supplied tothe address input register 111. In this case, the external clock and theinternal clock transferred to the address register are synchronized witheach other to thereby allow compensation for a signal delay in a clockinput path.

A plan view of a still further embodiment of a semiconductor integratedcircuit device according to the present invention is shown in FIG. 14.Although not restricted in particular, the semiconductor integratedcircuit device showing the present embodiment is intended for a staticRAM (Random Access Memory). A layout of rewirings, and bump electrodesand pads connected thereto is shown therein.

In a manner similar to the above even in the same drawing, bumpelectrodes 20, etc. are respectively indicated by ◯ and pads 22, etc.are respectively indicated by small □. These bump electrodes and padsare interconnected with each other by their corresponding rewirings 21and the like. Even in the present embodiment, the rewirings are dividedinto two types for a DC voltage and an AC signal according to thefunctions thereof. One rewiring layer 25 illustratively shown isidentical to the rewiring employed in the conventional wafer/level CSP(chip size package) and connects one bump electrode and one pad to eachother in a one-to-one correspondence. Each rewiring layer 25 is used forthe input of an address and a control signal and the input/output ofdata. These individual signal lines 25 are reduced in parasitic capacityand make use of rewiring layers each having a wiring width relativelyformed thin in association with a plurality of pads provided in highdensity in order to transfer digital signals transmitted through thesignal lines at high speed.

In the present embodiment, the rewiring layer is used to allow thesupply of power under low impedance. In the same drawing, rewiringlayers 21 each having a thick wiring width, which extend along chipperipheral portions at an upper half portion and a lower half portion ofa semiconductor chip, are provided to supply an internal stepped-downvoltage VDDI. Stepped-down voltages VDDI formed by debooster orstep-down circuits 23 indicated by dotted lines on both sides as viewedfrom side to side, of the central portion of the chip, are transmittedto their corresponding rewiring layers 21 through on chip wirings 24such as aluminum wiring. When a source voltage VDD is given as 3.3V, forexample, the stepped-down voltage VDDI is set to a low voltage like1.5V.

Of the rewirings other than the rewirings 21, rewirings each formed witha relatively thick wiring width except for the thin rewirings for thesignal input includes ones for supplying a circuit ground potential VSS,for example, or ones for supplying a source voltage VDD, and are set toa source voltage VDDQ for an output circuit and a circuit groundpotential VSSQ or the like in order to lessen the influence of powernoise in a manner similar to the above. A plurality of bump electrodesare provided for these, and the same voltage like the VSS or VDD issupplied from the bump electrodes. In the SRAM according to the presentembodiment, peripheral circuits are disposed in vertical and horizontalcentral portions of the chip, and a memory array is provided so as to bedispersed as four areas by such peripheral circuits.

A schematic cross-sectional view for describing a method ofmanufacturing the rewirings is shown in FIG. 15. In FIG. 15( a),polyimide corresponding to an organic insulating film is applied afterthe completion of a circuit on a semiconductor substrate (wafer). Anorganic insulating film having an opening is formed on an aluminum (Al)pad by a photolithography technology (photo and development) and bakedfor curing. In FIG. 15( b), a resist film is formed and processed by thephotolithography technology (photo and development) to form wiringpatterns for rewirings. In FIG. 15( c), Cu (Copper) is electroplatedafter cleaning. In FIG. 15( d), the resultant product is immersed in aresist film removing solution. In FIG. 15( e), an upper organicinsulating film is formed. Namely, polyimide is applied in the samemanner as described above and an upper organic insulating film having anopening at each bump electrode is formed by the photolithographytechnology (photo and development) and baked for curing.

A cross-sectional view showing another embodiment illustrative ofrewirings provided in a semiconductor integrated circuit deviceaccording to the present invention is shown in FIG. 16. Unillustratedcircuit elements and wirings are formed on one main surface side of asemiconductor chip. Of the wirings, pads 04 are formed of the wiringlying in the top layer. An organic insulating film 02 corresponding to afirst layer is formed except for openings for the pads 04. Although notrestricted in particular, the organic insulating film 02 is formed ofpolyimide.

A rewiring layer 05 used as a conductive layer for electricallyconnecting between at least two pads 04 formed on the main surface sideof the semiconductor chip 06 is formed on the organic insulating filmcorresponding to the first layer formed of such polyimide. Cu (Copper)posts are provided at portions where bump electrodes 03 are formed, ofthe surface of such a rewiring layer 05. An encapsulating resin 101 isformed on a portion other than the portions. Further, the bumpelectrodes 03 are provided on the surfaces of the Cu posts. As the bumpelectrodes 03, at least two are provided for one rewiring 05.

A vertical cross-sectional view of a device structure, which shows oneembodiment illustrative of a logic circuit and an external input/outputcircuit formed on a semiconductor chip that constitutes a semiconductorintegrated circuit device according to the present invention, isillustrated in FIG. 17. A p type well region 122 having a depth of 0.8μm is formed on a p type silicon substrate 120 having a resistivity of10 Ωcm. An n channel type transistor (also called “MOSFET” or “MISFET”)operated at a source voltage of 1.8V, which is separated by device orelement isolation regions 125, is formed, within the p type well region122, of an n type drain region 137, an n type source region 136, a thingate oxide film 127 having a thickness of 4 nm, and a gate electrode 130having a gate length of 0.2 μm, which comprises an n type polysiliconfilm having a thickness of 0.2 μm.

Within the p type well region 122, an n channel type transistor 5operated at a source voltage of 3.3V, which is separated by the deviceisolation regions 125, is formed of an n type drain region 139, an ntype source region 138, a gate oxide film 126 having a thickness of 8nm, and a gate electrode 131 having a gate length of 0.4 μm, whichcomprises an n type polysilicon film having a thickness of 0.2 μm.Although not shown in the drawing, a p channel type transistor, whichconstitutes a CMOS circuit in combination with the n channel typetransistor, is configured by forming an n type well region on the p typesilicon substrate 120 and forming a p type source region and a drainregion therein.

A silicon nitride film 140 having a thickness of 100 nm, which isdeposited by a CVD method, is disposed over the transistors 4 and 5 forthe formation of self-alignment contacts. Further, there are providedcontact plugs 142 provided at desired positions of a contact interlayerfilm 141 having a thickness of 1 μm, which is flattened by a CMP method,a first metal wiring 143 comprising an aluminum film having a thicknessof 0.5 μm, first interlayer plugs 145 provided at desired positions of afirst interlayer film 144 having a thickness of 1 μm, which is flattenedby the CMP method, a second layer metal wiring 146 comprising analuminum film having a thickness of 0.5 μm, a second interlayer plug 148provided at a desired position of a second interlayer film 147 having athickness of 1 μm, which is flattened by the CMP method, a third layermetal wiring 149 comprising an aluminum film having a thickness of 0.5μm, a third interlayer plug 151 provided at a desired position of athird interlayer film 150 having a thickness of 0.8 μm, and a fourthlayer metal wiring 152 comprising an aluminum film having a thickness of1 μm. The fourth layer metal wiring 152 is used even as an electrodesuch as a bonding pad or the like in addition to a metal wiringcorresponding to a top layer.

In a system LSI wherein a plurality of circuit blocks such as a memorycircuit, an external input/output device, etc. that constituteperipheral circuits of a CPU (Central Processing Unit) with the CPU asthe center, constitute a one-chip microcomputer or the like formed on asingle semiconductor substrate, the thickness of a gate oxide film foreach MIS (MOS) transistor is classified into two types. In the case ofcircuits each of which needs to ensure a certain degree of withstandvoltage (withstand voltage to breakdown of gate oxide film) with respectto an operating voltage of each MIS transistor, e.g., ones using DRAMsas an external input/output circuit, an analog input/output circuit anda memory circuit, an address selection MOSFET of each memory cell, ananalog/digital converter, a digital/analog converter, etc. respectivelyhave, although not restricted in particular, MIS transistors having agate length of 0.4 μm and a gate oxide film thickness of 8 nm where a0.2-μm process technology is used. On the other hand, circuits eachoperated with a stepped-down relatively low internal voltage as anoperating source, i.e., a logic circuit, an SRAM, and a CPU respectivelycomprise MIS transistors each having a gate length of 0.2 μm and a gateoxide film thickness of 4 nm.

FIGS. 18 and 19 are respectively cross-sectional views of the devicestructure, for describing one embodiment of a method of manufacturingrewirings for a semiconductor integrated circuit device according to thepresent invention. FIG. 18(A) shows a cross-section of a wafer which isin a state in which bonding pads 202 (202 a and 202 b) are formed on thesurface of a semiconductor chip 201 in which a large number of circuitelements are formed on a semiconductor substrate, and which is coveredwith a protective layer 203 except for openings for the bonding pads202. One shown in the same FIG. (A) is equivalent to the stage ofcompletion of the conventional wire bonding connecting wafer.

As shown in FIG. 18(B), a lower insulating layer 204 is formed on thesurface of the wafer. Portions of the bonding pads 202 (202 a and 202 b)are opened or defined in such a lower insulating film 204.

As shown in FIG. 18(C), a rewiring 205 is formed up to a position toform each bump electrode as viewed from the bonding pad 202 a, and atthe same time a rewiring layer 295 is formed even with respect to thepad 202 b dedicated for detection.

As shown in FIG. 18(D), a surface insulating layer 206 is formed, andimmediate upper portions of the bonding pads 202 (202 a and 202 b) atthe rewiring layers 205 and 295, and a portion for forming each bumpelectrode are exposed.

Further, as shown in FIG. 19(E), an under bump-electrode metal ormetallurgy 207 is formed in the bump electrode forming portion, andunder bump metallurgy layers 297 are simultaneously formed over thebonding pads 202 (202 a and 202 b). The under bump metallurgy layers 297just or directly over the bonding pads 202 (202 a and 202 b) formed inthe above-described manner result in a testing pad 209 a correspondingto each power or signal input/output bonding pad 202 a, and a testingpad 209 b corresponding to each test-dedicated bonding pad 202 b.

As shown in FIG. 19(F), the leading ends of probes 211 are brought intocontact with their corresponding testing pads 209 a and 209 b to performa probe test, whereby the relief of each defective product by use of theredundancy of a circuit, the selection of functions, the sorting ofnon-defective products and defective products, etc. are executed.

As shown in FIG. 19(G), a bump electrode 208 is formed on the under bumpmetallurgy 207 by solder, and the completed wafer is cut so as to beseparated into each individual chips (dicing), thereby obtainingflip-chip type semiconductor integrated circuit devices. While aluminumor an aluminum alloy is normally used as a material for the bonding pad202 or its surface, copper or another metal may be used according to thetype of a wiring material used inside a semiconductor elemental device.

In addition to inorganic films such as a silicon oxide film, a siliconnitride film, etc., an organic film like polyimide, and a combination ofthese are used as the material for the protective layer 203. Thematerial for the lower insulating layer 204 may preferably use organicmaterials or substances having low elastic modulus (low modulus ofelasticity) and low permittivity, like polyimide, a fluorocarbon resin,various elastomer materials to relax a stress (state ofstress/distortion) which acts on the bump electrode 208 due to thedifference in thermal expansion between a semiconductor integratedcircuit device and a printed circuit board after the implementation ofthe substrate, and reduce the capacitance of the relocation wiring 205.Here, as the elastomer materials, may be mentioned, for example, siliconand acrylic rubber materials, a polymeric material having low elasticmodulus, which has blended these rubber materials, etc.

The lower insulating layer 204 is formed by spin coating using varnish,printing or film bonding. The thickness of the lower insulating layer204 may preferably be about 3 μm or more from the viewpoint of thestress and the reduction in capacitance. However, when the organic filmis used for the protective layer 203, the lower insulating layer 204 ismade thinner than it or may be omitted.

A three-layer wiring structure wherein a chromium, titanium, nickel, anickel alloy or the like having a thickness of from about 0.1 μm toabout 0.5 μm is stacked or layered on the upper and lower surfaces ofcopper or a steel alloy having a thickness of about 1 μm to about 5 μm,for example, is used for the relocation wiring 205. Further, aluminumand its alloy may be used therefor.

Organic materials having low elastic modulus, like polyimide, an epoxyresin, a fluorocarbon resin, and various elastomer materials maypreferably be used as the material for the surface insulating layer 206to relax the stress which acts on the bump electrode 208. A flexible onemay be used as the insulating film (further insulating film) below therewiring to absorb the stress that acts on the bump electrode. The upperinsulating film 206 may select a material relatively harder than thelower insulating film 204 from the viewpoint of its protection.Described specifically, the upper insulating film 206 and the lowerinsulating film 204 are respectively formed of a photosensitivepolyimide resin film. The amount of a solvent, molecular weight, thecontent of a filler, etc. prior to heat treatment (cure) are changed tothereby make it possible to change the final hardness (elastic modulus)of the film thereof. Further, the upper and lower insulating films maybe formed of materials different from each other. In this case, theupper insulating film 206 and the lower insulating film 204 areconsidered to be formed of, for example, an epoxy resin and a polyimideresin respectively.

As the under bump metallurgy 207, a metal having a high solder barrierproperty, such as chromium, nickel, nickel/tungsten, nickel/copper orthe like may preferably be formed with a thickness of about 0.3 μm toabout 3 μm. Further, a golden thin-film layer having a thickness ofabout 0.1 μm may preferably be formed on the surface thereof to ensurewettability of solder and electrical connectability to each probe. Thesolder bump electrode 208 can be formed by printing solder paste on theunder solder bump metallurgy 207 or transferring a solder ball molded toa predetermined size in advance and thereafter effecting reflow on it.

The testing pads 209 are provided just or directly over both of thepower-supply or signal input/output bonding pad 202 a and the bondingpad 202 b for probe testing, thereby making it possible to execute theprobe test after the rewiring process. It is therefore possible toprevent degradation in connection reliability due to damage of eachbonding pad 202 prior to the rewiring process. Particularly when therewirings are used as wirings for distributing a signal as in thepresent embodiment, the probe test thereof becomes important.

Since an inspection is done without applying the probe 211 to thealready-formed solder bump electrode 208 in the above configuration, thesolder bump electrode 208 can be prevented from deforming. It is alsopossible to prevent damage of the probe 211 due to the application ofthe probe decentered to a curved surface of the solder bump electrode208 to the solder bump electrode 208.

It is not necessary to apply the probe 211 to the under solder bumpmetallurgy 207 antecedent to the formation of the solder bump electrode208 in the above configuration. Therefore, there is no fear that thelayer for enhancing solder wettability, such as gold or the like formedon the surface of the under solder bump metallurgy 207, and the solderbarrier metal layer placed below the layer are endamaged, thus making itpossible to prevent degradation in connection reliability to solder.

In the above-described configuration, owing to the arrangement of thetesting pads 209 in a row, an inexpensive cantilever type probe can beused as the probe 211 as shown in FIG. 19(F). Further, since the bondingpads 202 on the normal wire-bonding wafer with no rewirings appliedthereto, and the testing pads 209 described in the present embodimentare identical to one another in position within a chip plane, the normalwire-bonding wafer and the probe 211 can also be shared therebetween.

Since the testing pads 209 enter into projected areas of the bondingpads 202 in the aforementioned flip-chip type semiconductor integratedcircuit device, an increase in capacitance due to the addition of thetesting pads 209 is next to nothing. Incidentally, owing to theprovision of only the testing pads 209 without providing the bumpelectrodes for some bonding pads 202 b, the probe test can be executedafter the rewiring process without increasing the number of solderbumps.

Processes for manufacturing a flip-chip type semiconductor integratedcircuit device according to the present invention are shown in FIGS. 20through 24 every stages in the form of perspective views. FIG. 20 showsa completed stage of a conventional wire bonding connecting wafer.Namely, FIG. 20 is a view showing the whole span of a wafer 220 placedin the state shown in FIG. 18(A). The bonding pads 202 are respectivelyformed in respective chips 210.

In order to manufacture the flip-chip type semiconductor integratedcircuit device, lower insulating layers 204, rewirings 205, surfaceinsulating layers 206 and under bump metals or metallurgies 207, etc.are formed on the wafer 220 shown in FIG. 20 as illustrated in FIGS.18(B), 18(C) and 18(D) and 19(E) by way of example. Thus, such a wafer220 as shown in FIG. 21 placed in a state in which the under bumpmetallurgies 207 are formed, is obtained. The state of FIG. 21 isequivalent to the state of FIG. 19 as viewed in the form of across-section.

Next, as shown in FIG. 22, a plurality of probes 211 are positioned sothat their leading ends or tips are simultaneously brought into contactwith a plurality of testing pads 209 (unillustrated in FIG. 22) on thewafer 220. In this condition, probe tests are carried out through theuse of a fixed probe card 221. The plurality of probes 211 aresimultaneously brought into contact with the plurality of testing pads209 to thereby simultaneously test or inspect the testing pads 209corresponding to one chip 210 or plural chips 210 and inspect them whiletheir contact positions are being shifted successively, whereby theprobe tests are effected on all the chips 210 on the wafer 220. At thistime, the selection of functions and the relief of defects can beperformed simultaneously or successively by using the same or similaranother probe card 221.

A process for forming solder bump electrodes will next be explained byreference to FIG. 23 with a solder paste printing system as an example.A solder printing mask 222 in which openings 223 are defined inassociation with the layouts of under bump metallurgies 207 on thesurface of a wafer 220 as shown in the drawing, is superimposed on thewafer 220 in alignment with it, and solder paste 225 is printed thereonby a squeegee 224. In a state placed immediately after the printing, thesolder paste 225 is evenly printed on an area slightly wider than theunder bump metallurgies 207 as shown by a cross-sectional view in thedrawing. When this wafer is reflow-heated to melt the solder paste 225,solder is aggregated spherically to form solder bump electrodes 208.

The wafer 220 subsequent to the formation of the bump electrodes 208 iscut and separated into pieces of chips 210 by a dicing blade 226 asshown in FIG. 24, whereby completed products each corresponding to theflip-chip type semiconductor integrated circuit device can be obtained.The completed products are further subjected to a burn-in inspection andvarious final inspections for their performance, external appearance,etc. as needed. After they are subjected to predetermined markings andpackaged, they are shipped or delivered.

FIG. 25 shows manufacturing process flows subsequent to a rewiringforming process of a flip-chip type semiconductor integrated circuitdevice according to the present invention in the form of four types of(a), (b), (c) and (d). If the structure shown in FIG. 19(G) is taken asone example, then the manufacturing flows shown in the same drawinginclude respective process steps: a rewiring forming S1 for forming eachrewiring 205 on an insulating layer 204, a surface insulating layerforming S2 for forming such an insulating layer as designated at numeral206, an under bump metallurgy forming S3 for forming such an under bumpmetallurgy as designated at numeral 207 and an under metallurgy 297 foreach testing pad 209, etc., a function selecting S4 like mode stettingbased on the program for the antifuse 1, a probe testing S5, a defectrelieving S6 like defective-bit replacement based on the program for theantifuse 1, a bump forming S7 for forming each bump electrode, a piececutting (dicing) S8 for cutting out chips from a wafer, a burn-in S9,and a final testing S10.

The manufacturing flow shown in FIG. 25( a) corresponds to the burn-inS9, i.e., a manufacturing flow for performing a continuous operationtest at a high temperature in chip units after the completion of thepiece cutting S8. Since the interval between solder bump electrodes ismade wider than the interval (of about 60 μm to about 150 μm) betweenbonding pads by each rewiring in the flip-chip type semiconductorintegrated circuit device (about 0.5 mm to about 1.0 mm), the burn-in ineach chip unit can easily be carried out through the use of each burn-insocket employed in a BGA (Ball Grid Array) type CSP (Chip Size Package).Namely, the bump electrodes are formed on the chip in advance prior tothe burn-in step, and arrangement patterns for the bump electrodes arerespectively associated with electrode arrangement patterns for theburn-in sockets. Thus, since it is not necessary to newly preparecustom-engineered burn-in sockets, the cost for the assembly of theflip-chip type semiconductor integrated circuit device can be reduced.

Even when the burn-in sockets with the bump electrodes used asconnecting terminals are not used, electrical connections for burn-incan be preformed by use of the testing pads 209. In this case,narrow-pitch type expensive burn-in probes capable of probing arenecessary for the testing pads placed between the bump electrodes,whereas the deformation of each solder bump electrode 208 due to socketcontact at a high temperature can be prevented.

In the manufacturing flows shown in FIGS. 25( b) and 25(c), the burn-inS9 are carried out in a wafer stage before the piece cutting S8. Inparticular, FIG. 25( b) is a manufacturing flow for performing burn-inbefore the formation of the solder bump electrodes by use of the testingpads 209 or the under bump metallurgies 207 antecedent to the formationof the solder bump electrodes 208. Since the electrical connections forburn-in are performed without having to use the bump electrodes, it ispossible to prevent the deformation of each solder bump electrode due tothe contact of each burn-in socket under a high-temperature environment.Further, since the burn-in is performed in a flat stage antecedent tothe formation of each solder bump electrode, a burn-in probe like asocket can easily be applied to each testing pad 209 without bringingthe solder bump electrodes 208 into obstacles. Since the burn-in is donein the wafer stage, a plurality of chips can be subjected to burn-in ina lump and throughput for testing can be improved.

FIG. 25( c) shows a manufacturing flow for performing burn-in after theformation of the solder bump electrodes. The burn-in probe is broughtinto contact with each solder bump electrode 208. When the burn-in probeis brought into contact with the solder bump electrode 208, the solderbump electrode 208 is easy to deform upon burn-in. However, there is inno danger of endamaging each under bump metallurgy 207 or developing asurface deterioration in the under bump metallurgy 207. It is thuspossible to form high-reliable under bump metallurgies and rewirings.Since the burn-in is performed in the wafer stage in the same manner asFIG. 25( b) even in this case, throughput for testing can be improved.

The manufacturing flow shown in FIG. 25( d) is a manufacturing flow inwhich the steps corresponding to the surface insulating layer forming S2in the respective flows shown in FIGS. 25( a) through 25(c) are replacedby a step corresponding to an under bump metallurgy forming S3. Processsteps subsequent to a function selecting step are common to any of themanufacturing flows shown in FIGS. 25( a) through 25(c). Therelationship between FIGS. 25( a) through 25(c) and FIG. 25( d) is asfollows. Since the rewiring 205 and the under bump metallurgy 207 areformed in the same process under the manufacturing flow shown in FIG.25( d), the cost for the formation of the under bump metallurgy can bereduced as compared with the manufacturing flows shown in FIGS. 25( a)through 25(c).

When circuit elements of a semiconductor integrated circuit device aremanufactured in a fully-established process and percent defective islow, the burn-in might be omitted. In this case, the respectivemanufacturing flows shown in FIGS. 25( a) through 25(c) are preciselyidentical to one another and hence there is no difference.

In any of the respective manufacturing process flows shown in FIG. 25,the function selecting S4, t he probe testing S5 and the defectrelieving S6 are carried out in succession. When an antifuse is used inthe function selecting S4 and the defect relieving S6, any of thesethree steps can be performed by bringing each probe into contact withthe wafer and thereby performing electrical processing (unaccompanied byfuse cut-out by laser and a change in rewiring) alone. Therefore, thethree steps can be processed in a batch with one probing (i.e., withoutperforming probing again after probing on other chips), and hence theprocesses can be simplified. In this case, the function selection andthe defect relief can also be considered with being included in a broadprobe test.

In any of the respective manufacturing process flows shown in FIG. 25,the solder bump electrode forming S9 are collectively carried out in thewafer stage antecedent to the piece cutting S8. Thus, the solder bumpelectrodes can be formed efficiently as compared with the conventionalBGA and CSP manufacturing processes for forming the solder bumpelectrodes every piece chips. Further, the execution of the three stepsof the function selecting S4, probe testing S5 and defect relieving S6prior to the solder bump electrode forming S7 makes it possible toeasily perform probing without protrusions from the solder bumps beingtaken as obstacles.

The function selecting S4 can also be carried out after the probetesting S5 or the defect relieving S6. However, if the functionselecting S4 is executed prior to the probe testing S5, then only apre-selected function may be tested upon the probe testing S5. It istherefore possible to reduce inspection items and improve inspectionefficiency. The function selection may be carried out by means of therewiring. Namely, the processes up to the formation of each circuit onthe wafer are set identical, and such a conventional bonding option thatthe bit configuration is set to ×16 bits, ×32 bits or ×64 bits or thelike according to the rewiring forming process in the example of theDRAM, may be executed by use of the rewirings.

The rate of demand between respective types obtained according to thefunction selecting S4 always changes according to the market situation.Thus, it is desirable to prepare stock in a state prior to the functionselection for the purpose of performing flexible support for the demandchange and minimizing the amount of stock every types. It is alsodesirable to cope with a step subsequent to the function selection in asshort periods as possible. Owing to the use of an antifuse for functionselection, the same rewiring patterns can be taken over all the typesand the stock can be kept in a state placed immediately before theformation of each bump electrode. Thus, the required types can bemanufactured in a short period according to the change in demand, andthe amount of the stock can be reduced.

In regard to the manufacturing flows described in FIG. 25, the functionselecting S4 based on the program element can be performed after thebump electrode forming S7 contrary to the above. In this case, it isnecessary to expose electrodes for respectively applying voltages toprogram elements onto the surface of a semiconductor integrated circuitdevice for the purpose of the function selection in a manner similar toprojecting or protruding electrodes. However, since each individualsemiconductor integrated circuit devices can be stocked in a state inwhich the wafer process has virtually been finished, except for aprocess attendant on the function selection, stock management is easy.

A schematic cross-sectional view of a still further embodiment of asemiconductor integrated circuit device according to the presentinvention is shown in FIGS. 26(A) and 26(B). Unillustrated circuitelements and wirings are formed on one main surface side of such asemiconductor chip as described above. Of the wirings, each pad isformed of the wiring lying in the top layer. The pad is connected to itscorresponding bump electrode by a rewiring used as a conductive layer asdescribed above. While omitted in the same drawing, an organicinsulating film corresponding to a first layer formed of polyimide isformed in a manner similar to the embodiment shown in FIG. 1 except foropenings for the pads formed thereat. Further, rewirings are formed onthe organic insulating film.

In the present embodiment, FIG. 26(A) is different from the embodimentshown in FIG. 1. One bump electrode and one pad are connected to eachother by a rewiring. On the other hand, rewirings shown in FIG. 26(B)are provided so as to intersect the rewiring shown in FIG. 26(A)although not restricted in particular. The rewiring connected to the padand the rewiring connected to the bump side are connected to each otherat the intersecting portion by means of a wiring such as the top Al(Aluminum) line formed in the same process as the pad. Therefore, therewiring shown in FIG. 26(A) is provided on the unillustrated organicinsulating film corresponding to the first layer on the top layer Alline for connecting the two rewirings.

As to the rewirings employed in the present embodiment, in addition tothe rewiring for connecting the pad and the bump in a one-to-onecorrespondence as shown in the drawing, the rewiring provided so as tointersect on the top Al line in FIG. 26(B) by way of example may be arewiring used as some of a signal line or a power supply line in amanner similar to the embodiment shown in FIG. 11, e.g., it may be asignal wiring for connecting a pad and a pad or a source or power wiringfor connecting a bump and a bump.

A schematic configurational view of a still further embodiment of asemiconductor integrated circuit device according to the presentinvention is shown in FIGS. 27(A) and 27(B). FIG. 27(A) shows aschematic sectional structure thereof, and FIG. 27(B) shows circuitpatterns, respectively. The present embodiment illustrates amodification of the embodiment shown in FIGS. 26(A) and 26(B). Wiringsformed on one main surface side of a semiconductor chip, which connectrewirings to each other, are utilized in combination with wirings placedbelow the top layer (M4), e.g., wirings M3 each corresponding to a thirdlayer in addition to the top layer (M4).

Where a rewiring extended so as to intersect as shown in FIG. 27(B), anda signal line or the like formed by the top layer M4 extended inparallel in a bump-to-pad connecting direction are provided between abump and a pad when the bump and pad are connected to each other asshown in FIG. 27(A) by way of example, wirings M3 each corresponding toa third layer provided therebelow are further used to form portionswhich intersect the M4.

According to FIG. 27(A), the pad is connected to one end of thecorresponding rewiring by a contact. The other end of the rewiring isconnected to one end of the corresponding M4 wiring by a contact, andthe other end of the M4 wiring is connected to one end of thecorresponding M3 wiring by a contact. The other end of the M3 wiring isconnected to one end of its corresponding M4 wiring by a contact.Consequently, first intersection is made to the signal line or the like.The other end of the M4 wiring is connected to one end of thecorresponding M3 wiring by a contact at the portion intersecting thesignal line or the like. The other end of the M3 wiring is connected toone end of the corresponding M4 wiring by a contact. By connecting theother end of the M4 wiring to its corresponding rewiring connected tothe bump, the pad and bump are electrically connected to each other.Incidentally, the other wiring (M4) and the rewiring at the intersectingportion are omitted from FIG. 27(A).

A plan view of a still further embodiment of a semiconductor integratedcircuit device according to the present invention is shown in FIG. 28.Although not restricted in particular, the semiconductor integratedcircuit device showing the present embodiment is intended for a memorycircuit like a static RAM. A layout of rewirings, and bump electrodesand pads connected thereto is shown therein.

In a manner similar to the above even in the same drawing, the bumpelectrodes are respectively indicated by ◯ and the pads are respectivelyindicated by small □. These bump electrodes and pads are interconnectedwith each other by their corresponding rewirings. Even in the presentembodiment, the rewirings are divided into two types for a DC voltageand an AC signal according to the functions thereof. The rewirings forthe AC signal are identical to the rewiring employed in the wafer/levelCSP and connects one bump electrode and one pad to each other in aone-to-one correspondence. Each wiring is used for the input of anaddress and a control signal and the input/output of data. Theserewirings for the signals are reduced in parasitic capacity and make useof rewiring layers each having a wiring width relatively formed thin inassociation with a plurality of pads provided in high density in orderto transfer signals transmitted through the rewirings at high speed.

Even in the present embodiment, the rewiring layer is used to enable thesupply of power under low impedance. In the same drawing, a rewiringlayer having a thick wiring width, which extends along a central portionof a semiconductor chip and a peripheral portion thereof, is provided tosupply a stepped-down voltage formed by an internal step down circuit.Stepped-down voltages formed by the debooster voltage circuits providedat both the right and left ends of the central portion of the chip aresupplied to the rewiring layer and distributed to the periphery of thechip by contacts as operating voltages for internal circuits. When thesource voltage is set as 3.3V, for example, the stepped-down voltage isgiven as a low voltage like 1.5V.

Two rewirings provided inside the step down voltage source line, whichextend along the longitudinal direction of the chip, are provided tosupply a circuit ground potential VSS. Incidentally, a source or powersupplied from outside is transferred to the step down circuit byunillustrated bumps and rewirings. Incidentally, when input/outputinterfaces operated by the external source or power exist, they aresupplied with power by the bumps, rewirings and internal wirings. Sincethese configurations are similar to the embodiment shown in FIG. 14,they will be omitted.

A plan view of a still further embodiment of a semiconductor integratedcircuit device according to the present invention is shown in FIG. 29.The semiconductor integrated circuit device showing the presentembodiment is a modification of the embodiment shown in FIG. 28. Thehalf of the memory chip shown in FIG. 28 is shown in the same drawing inenlarged form. Although not restricted in particular in the presentembodiment, rewirings for connecting one bump electrodes and one pads inone-to-one correspondences are caused to intersect each other.

Owing to such intersection, a change in function or the like isperformed according to a change in rewiring pattern while using thearrangement or sequence of the same bumps and pads, for example. Thiscan provide a function equivalent to the conventional bonding option orthe like, for example. Alternatively, at a specific signal, theintersecting portion described above is utilized so as to obtain areduction in parasitic capacity and the shortest distance with a viewtoward transferring a signal transmitted therethrough at high speed.Such a technology of intersecting the rewirings each other can beimplemented by utilizing the top wirings and their lower wirings formedon such semiconductor substrates as employed in the embodiments of FIGS.26 and 27.

Operations and effects obtained from the above embodiments are asfollows:

(1) An advantageous effect is obtained in that circuit elements andwirings constituting a circuit, and first electrodes electricallyconnected to such a circuit are provided on one main surface of asemiconductor substrate, an organic insulating film is formed on thecircuit except for surface portions of the first electrodes, first andsecond external connecting electrodes are provided on the organicinsulating film, and at least one conductive layer for electricallyconnecting the first and second external connecting electrodes and thefirst electrodes is mounted onto the organic insulating film, wherebysuch a conductive layer is available even as a satisfactory power supplypath, and the degree of freedom of the layout of circuits such as apower circuit formed on the semiconductor substrate can be enhanced.

(2) An advantageous effect is obtained in that in addition to the above,the area of each of the first and second external connecting electrodesis formed so as to become larger than that of each of the firstelectrodes, whereby external connecting means such as bump electrodes,etc. can be obtained while bringing the elements and wirings or the likeformed on the semiconductor substrate into high integration.

(3) An advantageous effect is obtained in that the conductive layer isformed of a rewiring in addition to the above, whereby a semiconductorintegrated circuit device can be completed in a wafer process.

(4) An advantageous effect is obtained in that in addition to the above,the conductive layer is formed so as to be substantially identical tothe length of one side of the quadrangular semiconductor substrate orlonger than that, whereby a source voltage or the like can efficientlybe supplied to the respective circuit elements formed on thesemiconductor substrate.

(5) An advantageous effect is obtained in that in addition to the above,the same voltage is applied to the first and second external connectingelectrodes to thereby enable the supply of a voltage at low impedance.

(6) An advantageous effect is obtained in that in addition to the above,a source voltage is supplied from each of the first and second externalconnecting electrodes to thereby enable the supply of the source voltageat low impedance, whereby the operation of the circuit formed on thesemiconductor substrate can be stabilized.

(7) An advantageous effect is obtained in that in addition to the above,a circuit ground voltage is supplied to each of the first and secondexternal connecting electrodes to thereby enable the supply of theground voltage at low impedance, whereby the stabilization of theoperation of the circuit formed on the semiconductor substrate can beachieved.

(8) An advantageous effect is obtained in that in addition to the above,second electrodes electrically connected to the circuit are furtherprovided on the one main surface, and the first and second externalconnecting electrodes and the first and second electrodes areelectrically connected to one another by the conductive layer, whereby auniform voltage can stably be supplied to each circuit element formed onthe semiconductor substrate.

(9) An advantageous effect is obtained in that in addition to the above,solder balls are provided for the first and second external connectingelectrodes to thereby enable the manufacture thereof in a wafer process,whereby the packaging of a semiconductor integrated circuit device canbe carried out simply and stably.

(10) An advantageous effect is obtained in that circuit elements andwirings constituting a circuit, and first and second electrodeselectrically connected to such a circuit are provided on one mainsurface of a semiconductor substrate, an organic insulating film isformed on the circuit except for openings on the surfaces of the firstand second electrodes, and at least one conductive layer forelectrically connecting the first and second electrodes is placed on theorganic insulating film, whereby the conductive layer can be used evenfor signal transfer, the degree of freedom of the layout of each circuitformed on the semiconductor substrate can be enhanced and the speedingup of operation can be achieved.

(11) An advantageous effect is obtained in that the conductive layer isformed of a rewiring in addition to the above to thereby enable theimplementation of a high-speed signal path in a wafer process.

(12) An advantageous effect is obtained in that in addition to theabove, first and second external connecting electrodes are furtherprovided on the organic insulating film, and the conductive layer isconnected to the first and second external connecting electrodes,whereby a uniform voltage can stably be supplied from the outside to thecircuit elements formed on the semiconductor substrate.

(13) An advantageous effect is obtained in that the first and secondexternal connecting electrodes are respectively configured as bumpelectrodes in addition to the above, thereby making it possible tocomplete a semiconductor integrated circuit device according to a waferprocess and realize high-density packaging on a printed circuit board.

(14) An advantageous effect is obtained in that the first and secondelectrodes are respectively formed as bonding pads, so that asemiconductor chip related thereto can be built into a semiconductorintegrated circuit device having lead terminals, thus making it possibleto implement diversified package forms of semiconductor chips.

(15) An advantageous effect is obtained in that the areas of the firstand second external connecting electrodes are set larger than those ofthe first and second electrodes in addition to the above, wherebyexternal connecting means such as bump electrodes, etc. can be obtainedwhile bringing the elements and wirings or the like formed on thesemiconductor substrate into high integration.

(16) An advantageous effect is obtained in that in addition to theabove, solder balls are provided for the first and second externalconnecting electrodes to thereby enable the manufacture thereof in awafer process, whereby the packaging of a semiconductor integratedcircuit device can be carried out simply and stably.

(17) An advantageous effect is obtained in that in addition to theabove, first external connecting electrodes are further provided on theorganic insulating film, the conductive layer is connected to each ofthe first external connecting electrodes, and external connectingelectrodes other than the first external connecting electrodes aredisconnected therefrom, thereby making it possible to effectively supplya voltage or signal to each circuit element formed on the semiconductorsubstrate by use of one external terminal.

(18) An advantageous effect is obtained in that a clock signal issupplied to the first external connecting electrodes in addition to theabove, thereby making it possible to reduce skews of clocks supplied toplural circuits formed on a semiconductor substrate and speed up eachcircuit.

(19) An advantageous effect is obtained in that in addition to theabove, a voltage forming circuit responsive to a first voltage isfurther provided on the one main surface of the semiconductor substrate,and the voltage forming circuit forms a second voltage different fromthe first voltage and transfers the second voltage through theconductive layer, whereby a power circuit formed on the semiconductorsubstrate can be simplified and laid out easily, and a uniform voltagecan be supplied stably.

(20) An advantageous effect is obtained in that in addition to theabove, a clock reproducing circuit responsive to a first clock isfurther provided on the one main surface of the semiconductor substrate,and the clock reproducing circuit outputs a second clock correspondingto the first clock and distributes it through the conductive layer,whereby an internal clock synchronized with a clock supplied fromoutside can be distributed to each circuit formed on the semiconductorsubstrate with efficiency.

(21) An advantageous effect is obtained in that in addition to theabove, the conductive layers are connected via the wirings provided onthe one main surface of the semiconductor substrate at parts thereof,whereby the conductive layers can be placed so as to intersect eachother, and signal and source lines can easily be laid out.

(22) An advantageous effect is obtained in that in addition to theabove, top-layer wirings formed on the one main surface of thesemiconductor substrate and wirings formed therebelow are utilized incombination as the wirings for connecting the conductive layers to oneanother, whereby the layout of signal and source lines can be madeeasier.

(23) An advantageous effect is obtained in that circuit elements andwirings constituting each circuit, and first and second electrodeselectrically connected to the circuit are provided on one main surfaceof a semiconductor substrate, an organic insulating film is formed onthe circuit except for surface portions of the first and secondelectrodes, first and second external connecting electrodes are providedon the organic insulating film, conductive layers for respectivelyelectrically connecting the first and second external connectingelectrodes and the first and second electrodes are placed on the organicinsulating film, and one of the conductive layers is connected to itscorresponding wiring provided on the one main surface of thesemiconductor substrate at a portion where they intersect, whereby thelayout of signal and source lines can be facilitated.

(24) An advantageous effect is obtained in that in addition to theabove, top-layer wirings formed on the one main surface of thesemiconductor substrate and wirings formed therebelow are utilized incombination as the wirings for connecting the conductive layers to oneanother, whereby the layout of signal and source lines can be madeeasier.

While the invention made above by the present inventors has beendescribed specifically based on the illustrated embodiments, theinvention of the present application is not limited to the embodiments.It is needless to say that various changes can be made thereto withinthe scope not departing from the substance thereof. For example, thestructure and material of each rewiring formed on the semiconductor chipcan take various embodiments. The present invention can be applied to atype in which a plurality of semiconductor integrated circuit devicesprovided with the bump electrodes are placed on one printed circuitboard to take a multi chip module configuration. Besides, the presentinvention can be applied even to a semiconductor integrated circuitdevice of such a multi chip package configuration that two semiconductorchips are assembled into a laminated structure to thereby form onesemiconductor integrated circuit device.

INDUSTRIAL APPLICABILITY

The present invention is widely available to a semiconductor integratedcircuit device formed up to a package in a wafer process.

1. A semiconductor integrated circuit device comprising: a semiconductorsubstrate; circuit elements and wirings which are provided on one mainsurface of the semiconductor substrate and constitute a circuit; firstand second electrodes provided on the one main surface and electricallyconnected to the circuit; an organic insulating film provided on thecircuit except for openings on the surfaces of the first and secondelectrodes; first and second external connecting electrodes provided onthe organic insulating film; and first and second conductive layers usedfor respectively electrically connecting the first and second externalconnecting electrodes to the first and second electrodes, wherein thefirst and second conductive layers adhere onto the organic insulatingfilm, and wherein the first conductive layer is connected to the wiringsprovided on the one main surface of the semiconductor substrate atportions intersecting the second conductive layer.
 2. The semiconductorintegrated circuit device according to claim 1, wherein the wiringsconnected to the first conductive layer include top-layer wirings formedon the one main surface lying on the semiconductor substrate, andwirings formed therebelow.
 3. A semiconductor integrated circuit device,comprising: a semiconductor substrate; circuit elements and wiringswhich are provided on one main surface of the semiconductor substrateand constitute a circuit; first and second electrodes provided on theone main surface and electrically connected to the circuit; an organicinsulating film provided on the circuit except for openings on thesurfaces of the first and second electrodes; first and second externalconnecting electrodes provided on the organic insulating film; and firstand second conductive layers used for respectively electricallyconnecting the first and second external connecting electrodes to thefirst and second electrodes, wherein the first and second conductivelayers adhere onto the organic insulating film, and wherein the firstconductive layer is connected to the wirings provided on the one mainsurface of the semiconductor substrate, and wherein the wirings whichare connected to the first conductive layer are intersected with thesecond conductive layer at a plurality of intersecting portions.
 4. Thesemiconductor integrated circuit device according to claim 3, whereinthe wirings connected to the first conductive layer include lower-layerwirings formed on the main surface of the semiconductor substrate andupper-layer wirings formed on the lower-layer wirings.